(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to the controlling of internal addresses of a semiconductor memory device in a parallel test mode.
(2) Description of the Related Art
In recent years, as semiconductor memory devices with a large storage capacity have been manufactured, the time required for testing them has risen exponentially. This is a problem that external clock synchronous type memories ("synchronous memories") also face.
One known technique for solving the problem of increased time for testing semiconductor memory devices is disclosed in Japanese Patent Application Kokai Publication No. Sho 61-122998 (Convention priority from U.S. patent application Ser. No. 646,654 filed on Aug. 31, 1984, which proposes a method of applying a data bit to a device terminal in a writing operation conducted during a test mode to write the data into a plurality of memory cells in parallel, reading the data stored in the plurality of memory cells in parallel, detecting data identicality, that is, whether all the data are identical or not.
Japanese Patent Application Kokai Publication No. Hei 3-283199 filed by the NEC Corporation proposes a semiconductor memory device which has a parallel test circuit for a plurality of cells and which is capable of outputting the data read out as 1-bit or multiple-bit data and includes a plurality of selectors for dividing the read out data into a plurality of groups and sequentially outputting bit data out of the divided data of the groups according to a control signal and a plurality of identicality detection circuits for detecting the identicality of the bits of the data inputted by the selectors during a test mode, and which further comprises a multiple-bit parallel test circuit for detecting the identicality of the outputs of the plurality of the identicality detection circuits during the test mode for a 1-bit data output and also the identicality of the data sequentially outputted by the plurality of selectors. More specifically, the above publication describes a circuit configuration wherein circuits necessary for both a 4-bit output arrangement (hereinafter referred to as "X4 arrangement") and a 16-bit output arrangement (hereinafter referred to as "X16 arrangement") are disposed on the same chip and the output of the identicality detection circuit for the X16 arrangement is used as an input of the identicality detection circuit for 4-bit data of the X4 arrangement.
FIG. 1 of the accompanying drawings illustrates a prior art synchronous memory comprising a multiple-cell parallel test circuit that can carry out a parallel test as disclosed in Japanese Patent Application Kokai Publication No. Hei 3-283199.
Referring to FIG. 1, this prior art synchronous memory comprises a command decoder 1 for receiving as inputs external control signals of RAS (Row Address Strobe), CAS (Column Address Strobe) and WE (Write Enable) and an external clock signal CLK, a burst counter 3 for receiving an output signal ENBL of the command decoder 1 and a plurality of external address signals Ai (A0, A1, A2, . . . , AN-1, AN) for outputting a plurality of internal address signals YPi (YP0, YP1, YP2, . . . , YPN-1, YPN) (and comprising a plurality of serially connected flip-flops for counting and outputting internal address signals from latched external address signals for a predetermined burst length (which will be described later)) and a column decoder 4 for decoding internal address signals YPi (i=2, 3, . . . , N) and for outputting a plurality of column selection lines YSW0, YSW1, etc.
The prior art synchronous memory also comprises a row decoder 5 for receiving a plurality of external address signals Ai (i=0 to N) and an output signal ACTIVE of the command decoder 1 and for outputting a plurality of word lines and a plurality of plate section signals, and a pair of shared sense amplifiers 8 each connected to four bit lines and two I/O bus pairs of ROTj, RONj (j=a, b, c, d, . . . ) for receiving column selection lines YSWn. Reference numeral 7 in FIG. 1 denotes selection plates for inputting an output signal of the decoder 4 and for outputting to a plurality of read/write bus.
Additionally, this prior art synchronous memory comprises a pulse generating circuit 2 for receiving an external clock signal CLK and an output signal ENLB of the command decoder 1 and for outputting a signal RENBL (read enable) and a signal WENBL (write enable), a precharge control circuit 10 for receiving a plate selection signal and output signals RENBL, WENBL of the pulse generating circuit 2 and for outputting a first data amplifier enable signal and an I/O bus precharge signal, a plurality of first data amplifiers 9 connected to the I/O bus pairs and the read/write bus pairs RWBSTn, RWBSNn (n=0, 1, . . . ) for receiving an output signal of the precharge control circuit 10, a plurality of second data amplifiers 11 for receiving the read/write bus pairs RWBSTn, RWBSNn and an output signal RENBL of the pulse generating circuit 2 and outputting data signals OUTn (n=0, 1, . . . ), and a detection circuit 18 for receiving four read/write bus pairs RWBSTn, RWBSNn, detecting the identicality of the four inputs and outputting a detection signal T01.
This prior art synchronous memory further comprises a decoder 13 for decoding internal address signals YP0, YP1 and outputting a selection signal, a selection circuit (selector) 14 for selecting an output data signal OUTn of the second data amplifier 11 and the detection signal T01 by a decode signal of the decoder 13 and a test mode enable signal TEST and outputting output signals DOUTj (j=0, 1, . . . ), a plurality of data-out buffers 16 for receiving an output signal of the selection circuit 14 and driving I/O pads DOj (j=0, 1, . . . ), a plurality of data-in buffers 17 for receiving data from the I/O pads DOj and outputting input data DINj (j=0, 1, . . . ), a selection circuit (selector) 15 for selecting a bus for the input data DINj of the data-in buffer 17 according to the decode signal of the decoder 13 and the test mode enable signal TEST and outputting input data signals INn (n=0, 1, . . . ), and a write amplifier 12 connected to the read/write bus pairs RWBSTn, RWBSNn for receiving the input data signals INn that are the outputs of the selection circuit 15.
Now, a write operation of the above described device, during the test mode, will be described.
During the test mode, all of the four write buses are selected by the selection circuit 15. As a result, the same data DINJ is written into the four read/write bus pairs RWBSTn, RWBSNn (n=j, j+1, j+2, j+3) and also into the four cells on the same column selection line YSW.
In a write operation during test mode, the four read buses are not selected by the selection circuit 15 and the output T01 of the detection circuit 18 (a detection signal obtained by detecting the identicality of the four inputs) is selected by the selection circuit 14, which in turn outputs it as an output data signal DOUTj.
FIG. 2 shows the waveform of a column selection line YSW in a write or read operation of the prior art synchronous memory of FIG. 1.
Referring to FIGS. 1 and 2, when the number of data successively written in or read out (referred to as "burst length") is "4", a write or read command (CMD "WRITE" or "READ") is taken in at the rising edge of an external clock signal CLK (equivalent to ICLK (clock signal introduced into the memory)) in cycle C1 and an external address signal Ai (i=0 to N) is latched to the burst counter 3 by a signal ENBL that is an output of the command decoder 1, which burst counter 3 then outputs an internal address signal YPi.
In the example of FIG. 2, the internal address YPi i=0 to N) is set to YP=0.
From cycle C2 onwards, the burst counter 3 operates at each and every rising edge of the external clock signal CLK to count the internal address signals YP as 1, 2, 3 (that is, (YP0, YP1) becomes (1, 0), (0, 1), (1, 1) as the cycle moves on).
The above operation also takes place for executing a write or read command (CMD "WRITE" or "READ") upon the entry into the test mode (CMD "TEST ENTRY") (cycles C6 to C9).
As shown in FIG. 1, the lower order 2-bits YP0, YP1 (YP0 is the least significant bit) of the internal address signal outputted by the burst counter 3 are not inputted to the column decoder 4 but outputted to the selection circuit 14 or 15 through the decoder 13 for the sake of saving the operating current so that no switching operation is carried out on the column selection lines YSW when the burst length is "4" as shown in FIG. 2 (in other words, YSW is fixed to Y0).
With the prior art synchronous memory of FIG. 1, the column selection line YSW undergoes no switching operation during the burst when the burst length is "4" even during the test mode. Therefore, four write-in or read-out operations are conducted successively on the same cell in a 4-bit parallel test so far as to render the parallel test ineffective. In other words, since the combination of four (X4) input/output (I/O) column addresses (Y addresses) is the same as the combination of the four column addresses of the four data during the burst, the four successive data during the burst give rise to an access to four cells of the same column address (as the column selection line YSW is fixed), the parallel test cannot achieve the objective of improved efficiency, and thus, the effect of the test is lost.
The above problem is not solved by the arrangements disclosed in the Japanese Patent Application Kokai Publication Nos. Sho 61-122998 and Hei 3-283199.